Instruction Set Research Articles

Science lab safety goes immersive: An ecological media-comparison study with gender analyses assessing iVR’s learning effectiveness

We conducted a media-comparison study in ecologically valid settings to understand immersive virtual reality’s (iVR’s) instructional effectiveness in a university science course. We tested how complementing regular science lab safety instruction with interactive iVR simulation, desktop simulation, or the re-viewing of a text-heavy manual compare with each other in terms of knowledge-related and affective learning outcomes. We also explored gender differences in the outcomes across these instructional conditions. 102 undergraduates (51 females) were randomly assigned to one of the instructional conditions. Throughout the one-day course, all students received the same set of instructions, demonstrations, and hands-on lab safety training except for the following: the iVR group engaged with HMD-based interactive lab safety iVR training simulation; the desktop group interacted with the same simulation on a laptop, whereas the remaining group re-viewed the text-heavy course material in detail. Topic knowledge-related and self-report affective data were collected before and immediately after the course. Statistical analyses revealed that: (i) all three instructional modes helped students gain significant lab safety knowledge, (ii) there were several significant between-group differences in multiple affective measures, and (iii) the instructional modes affected/benefited the two genders considerably differently. Besides extending previous findings, the strong ecological grounding of our results adds important insights into real-life implications of integrating different media in undergraduate education. Our gender-related findings merely scratch the surface on the complex issue of “designing for diversity”, inviting scaled-up efforts to develop more equitable technology-enhanced science learning settings to address the cognitive-affective needs of different genders and other diversities.

R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA

Emerging data-driven applications in the embedded, e-Health, and internet of things (IoT) domain require complex on-device signal analysis and data reduction to maximize energy efficiency on these energy-constrained devices. Coarse-grained reconfigurable architectures (CGRAs) have been proposed as a good compromise between flexibility and energy efficiency for ultra-low power (ULP) signal processing. Existing CGRAs are often specialized and domain-specific or can only accelerate simple kernels, which makes accelerating complete applications on a CGRA while maintaining high energy efficiency an open issue. Moreover, the lack of instruction set architecture (ISA) standardization across CGRAs makes code generation using current compiler technology a major challenge. This work introduces R-Blocks; a ULP CGRA with HW/SW co-design tool-flow based on the OpenASIP toolset. This CGRA is extremely flexible due to its well-established VLIW-SIMD execution model and support for flexible SIMD-processing, while maintaining an extremely high energy efficiency using software bypassing, optimized instruction delivery, and local scratchpad memories. R-Blocks is synthesized in a commercial 22-nm FD-SOI technology and achieves a full-system energy efficiency of 115 MOPS/mW on a common FFT benchmark, 1.45 × higher than a highly tuned embedded RISC-V processor. Comparable energy efficiency is obtained on multiple complex workloads, making R-Blocks a promising acceleration target for general-purpose computing.

BiGResi: Robust bit-level fault injection framework for assessing intrinsic software resilience against soft errors

Radiation-induced soft errors, despite rare, pose a significant threat to the reliability of systems. Assessing the intrinsic resilience of software to soft errors is therefore essential for building fault-tolerant systems cost-effectively. Analytical models, while fast, can be imprecise. In contrast, Fault Injection (FI) has been successfully applied as a mature method for reliability assessment. While high-level FI offers less accuracy, existing low-level techniques can enhance resilience assessment accuracy by sacrificing some desirable features like fault coverage and intrusiveness. Furthermore, these techniques are often driven by random FI campaigns, making establishing a clear correlation between application characteristics and resilience challenging. This paper presents BiGResi, a versatile software-based framework for assessing software resilience. BiGResi overcomes the limitations of random, instruction type-agnostic FI techniques by evaluating resilience at a low-level granularity, considering instruction type and bit location. Furthermore, it targets the instruction set architecture (ISA), enhancing assessment accuracy by revealing architecturally visible faults. BiGResi employs a timing-based FI mechanism with negligible modifications to the target software, minimizing intrusiveness and ensuring near-native speed. BiGResi’s accuracy is empirically evaluated through many FI campaigns targeting different benchmarks with diverse characteristics. We observed that instruction types, ISA encoding bits, and bit location are key factors to consider when assessing software resilience. Finally, BiGResi’s effectiveness is demonstrated by selectively applying instruction protection, resulting in an average reduction of silent data corruptions (SDCs) by 73.80%, with a performance overhead of 15.46%. Furthermore, allowing a slightly higher overhead of 22% can improve the SDC detection rate by up to 93.83%.

Effects of flipped English learning designs on learning outcomes and cognitive load: Workload of out‐of‐class activities versus during‐class activities

AbstractBackgroundSome studies have researched the correlation between flipped learning and cognitive learning outcomes; however, there is a paucity of research elaborating on the effects of flipped language learning on cognitive load (CL).ObjectivesThis study investigates the effects of using flipped learning designs (student‐led, teacher‐led and collaboration‐led) on learning outcomes and CL management during out‐of‐class activities versus during‐class activities.MethodsA mixed methods research was used to concurrently triangulate different strands of data on the effects of flipped learning designs on English as foreign language (EFL) learners' learning outcomes and CL. A total of 122 EFL learners were randomly assigned to either the control or experimental group and participated in the study. The interpretations were made based on running one‐way analysis of variance between four groups.Results and ConclusionThis study evidenced the efficacy of the interactive use of collaboration‐led flipped learning design over student‐led and teacher‐led designs for improving learning outcomes and lowering CL during computer‐assisted language learning (CALL) course.Pedagogically, CALL practitioners need to develop and integrate a well‐organized combination of student‐led and teacher‐led flipped learning activities for during‐class and out‐of‐class phases with respect to the CL and learning material complexity, while also considering the specific contexts and goals of their instructional settings. Theoretically, the results indicate the necessity of merging active learning and sociocultural theories into an instructional design to take advantage of the identified affordances of flipped language learning approach in terms of psychological effects (CL management) and learning effects (CALL outcomes).

THE DESIGN OF THE PIPELINED RISC-V PROCESSOR WITH THE HARDWARE COPROCESSOR OF DIGITAL SIGNAL PROCESSING

Context. The digital signal processing is applied in many fields of science, technology and human activity. One of the ways of implementing algorithms of digital signal processing is the development of coprocessors as an integral part of well-known architectures.
 In the case of developing a pipelined device, the presented approach will allow to use software and hardware tools of the appropriate architecture, provide the faster execution of signal processing algorithms, reduce the number of cycles and memory accesses.
 Objective. Objectives are design and characterization study of a pipelined RISC-V processor and coprocessor of digital signal processing which performs fast Fourier transform.
 Method. Analyzing technical literature and existing decisions allow to assess advantages and disadvantages of modern developments and on the basis of which to form the relevance of the selected topic. Model designing and simulation results allow to examine a model efficiency, to determine weak components’ parts and to improve model parameters.
 Results. The pipelined RISC-V processor has been designed which executes a basic set of instructions. Execution time of assembly program on the single-cycled and the pipelined processors have been analyzed. According to the results, the test program on the pipelined processor is executed in 29 cycles, while on the single-cycle processor it takes 60 cycles. The structure of the coprocessor for the fast Fourier transform algorithm and a set of processor instructions that allow working with the coprocessor have been developed. The number of cycles of the coprocessor based on Radix-2 fast Fourier transform algorithm for 512 points is 2358 cycles, and for 1024 points is 5180 cycles.
 Conclusions. Conducted researches and calculations have showed that the application of the developed hardware coprocessor reduces the fast Fourier transform algorithm execution time and the load of the pipelined processor during calculations.

Design and fabrication of silicone cleft lip simulation model for personalized surgical training

Purpose of the studyTo elucidate the design and fabrication methodologies employed in creating a personalized cleft lip simulation model, primarily intended for enhancing surgical training and diverse applications. The research further seeks to assess the viability of integrating this simulation model into undergraduate oral experiments and instructional settings. Study designFacial data from individuals with cleft lip conditions were acquired using a scanner. Subsequent stages involved reverse engineering and the utilization of 3D printing technology to generate a cleft lip silicone simulation model. The molding process entailed injecting the silicone into a polylactic acid mold. The study enrolled 53 undergraduate students majoring in dentistry, who were randomly assigned to either a control or experimental group. A dedicated instructor guided each group independently, employing a combination of multiple-choice tests and surveys to gauge real-time evaluations and discern inter-group disparities. Results and conclusionsThe study successfully designed and produced a personalized cleft lip simulation model, demonstrating notable efficacy in the context of cleft lip experimental teaching. Statistical analysis revealed a significant difference (P<0.05) in the scores of the experimental group students on multiple-choice questions pertaining to cleft lip surgical procedures. Survey outcomes indicated that the experimental group students exhibited higher confidence levels in cleft lip surgery, as reflected in their responses to relevant questions, compared to the traditional group. These differences were statistically significant (P<0.05). The simulation model developed in this study emerges as a reliable and cost-effective training and teaching tool for cleft lip surgery.

PTME: A Regular Expression Matching Engine Based on Speculation and Enumerative Computation on FPGA

Fast regular expression matching is an essential task for deep packet inspection. In previous works, the regular expression matching engine on FPGA struggled to achieve an ideal balance between resource consumption and throughput. Speculation and enumerative computation exploits the statistical properties of deterministic finite automata, allowing for more efficient pattern matching. Existing related designs mostly revolve around vector instructions and multiple processors/cores or SIMD instruction sets, with a lack of implementation on FPGA platforms. We design a parallelized two-character matching engine on FPGA for efficiently fast filtering off fields with no pattern features. We transform the state transitions with sequential dependencies to the existing problem of elements in one set, enabling the proposed design to achieve high throughput with low resource consumption and support dynamic updates. Results show that compared with the traditional DFA matching, with a maximum resource consumption of 25% for on-chip FFs (74323/1045440) and LUTs (123902/522720), there is an improvement in throughput of 8.08-229.96 × speedup and 87.61-99.56% speed-up(percentage improvement) for normal traffic, and 11.73-39.59 × speedup and 91.47-97.47% speed-up(percentage improvement) for traffic with high-frequency match hits. Compared with the state-of-the-art similar implementation, our circuit on a single FPGA chip is superior to existing multi-core designs.

Examining Chinese teachers’ emotional vulnerability of teaching international students in an English medium instruction programme

Despite the fact that a growing number of studies have begun to focus on stakeholders' emotions in English medium instruction (EMI) settings, little is known, particularly about teachers' emotional vulnerability in EMI teaching. Situating teachers' emotional vulnerability as a sociocultural and ideological construct, this study seeks to investigate Chinese EMI teachers' emotional vulnerability of teaching international students in Southwest China. Based on a larger critical sociolinguistic ethnography, the findings reveal a slew of social, ideological, institutional, and personal factors that mediate Chinese EMI teachers' emotional vulnerability, indicating that their emotional vulnerability is largely influenced by the discourses of neoliberalism and performativity, which are dominated by the ideology of English hegemony, top-down evaluation mechanisms, and power relations. Simultaneously, Chinese EMI teachers' emotional vulnerability also can be transformed into agencies for possible alternatives. The paper concludes with some practical implications for mitigating the negative effects of emotional vulnerability on EMI teachers. The article contributes to raise a greater recognition of teachers' emotional vulnerability in EMI higher education contexts by sparking a critical discussion about how to promote the awareness of stakeholders’ emotional vulnerability and well being in policy making and curriculum design.

An Integrated Instruction and a Dynamic Fuzzy Inference System for Evaluating the Acquirement of Skills through Learning Activities by Higher Middle Education Students in Mexico

Background: The evaluation of the development of a student’s abilities and skills through a learning activity is a topic strongly questioned by the education system in Mexico. Several instruments have been developed to achieve said evaluation. However, these involve both qualitative and subjective assessment, thereby avoiding the possibility of unambiguously verifying the development of a student’s aptitudes. Methods: We developed a new instrument composed of an integrated instruction and a dynamic fuzzy inference system. Integrated instruction is a table that contains a set of instructions and a set of indicators that make it possible to evaluate knowledge, procedure, and attitude without establishing qualitative or subjective criteria to rank them. The dynamic fuzzy inference system assesses indicators under a criterion to demonstrate the development of a student’s abilities and skills. Results: The method was applied to three different learning activities, where the assessment was precise and transparent for the student, contributing to an extraordinary identification of the acquainted knowledge, procedure, and attitude that the student displayed to develop the activity. Conclusions: Our instrument evaluates the development of abilities and skills without ambiguity or subjectivity, making efficient feedback possible and allowing it to be perfected without difficulties for future adaptations.

Design and implementation of hardware-software architecture based on hashes for SPHINCS+

Advances in quantum computing have posed a future threat to today’s cryptography. With the advent of these quantum computers, security could be compromised. Therefore, the National Institute of Standards and Technology (NIST) has issued a request for proposals to standardize algorithms for post-quantum cryptography (PQC), which is considered difficult to solve for both classical and quantum computers. Among the proposed technologies, the most popular choices are lattice-based (shortest vector problem) and hash-based approaches. Other important categories are public key cryptography (PKE) and digital signatures. Within the realm of digital signatures lies SPHINCS+. However, there are few implementations of this scheme in hardware architectures. In this article, we present a hardware-software architecture for the SPHINCS+ scheme. We utilized a free RISC-V (Reduced Instruction Set Computer) processor synthesized on a Field Programmable Gate Array (FPGA), primarily integrating two accelerator modules for Keccak-1600 and the Haraka hash function. Additionally, modifications were made to the processor to accommodate the execution of these added modules. Our implementation yielded a 15-fold increase in performance with the SHAKE-256 function and nearly 90-fold improvement when using Haraka, compared to the reference software. Moreover, it is more compact compared to related works. This implementation was realized on a Xilinx FPGA Arty S7: Spartan-7.

Guide for authors: jCEC Template 2024

This document gives formatting instructions for authors preparing articles for publication in the jCEC journal.  The authors must follow the instructions given in the document for the articles to be published.  You can use this document as both an instruction set and as a template into which you can type your own text. Abstract should be no longer than 1000 characters including spaces (or from 200 to 300 words). It gives a brief summary of the content of the main objective, the methods, the results obtained and major conclusions. Translation of the abstract to an appropriate language must be provided here. Please choose either Portuguese, French or Spanish, and adapt your list of keywords accordingly. 

Benchmarking Large Language Models on Controllable Generation under Diversified Instructions

While large language models (LLMs) have exhibited impressive instruction-following capabilities, it is still unclear whether and to what extent they can respond to explicit constraints that might be entailed in various instructions. As a significant aspect of LLM alignment, it is thus important to formulate such a specialized set of instructions as well as investigate the resulting behavior of LLMs. To address this vacancy, we propose a new benchmark CoDI-Eval to systematically and comprehensively evaluate LLMs' responses to instructions with various constraints. We construct a large collection of constraints-attributed instructions as a test suite focused on both generalization and coverage. Specifically, we advocate an instruction diversification process to synthesize diverse forms of constraint expression and also deliberate the candidate task taxonomy with even finer-grained sub-categories. Finally, we automate the entire evaluation process to facilitate further developments. Different from existing studies on controllable text generation, CoDI-Eval extends the scope to the prevalent instruction-following paradigm for the first time. We provide extensive evaluations of representative LLMs (e.g., ChatGPT, Vicuna) on CoDI-Eval, revealing their limitations in following instructions with specific constraints and there is still a significant gap between open-source and commercial closed-source LLMs. We believe this benchmark will facilitate research into improving the controllability of LLMs' responses to instructions. Our data and code are available at https://github.com/Xt-cyh/CoDI-Eval.

An Instruction Inflation Analyzing Framework for Dynamic Binary Translators

Dynamic binary translators (DBTs) are widely used to migrate applications between different instruction set architectures (ISAs). Despite extensive research to improve DBT performance, noticeable overhead remains, preventing near-native performance, especially when translating from complex instruction set computer (CISC) to reduced instruction set computer (RISC). For computational workloads, the main overhead stems from translated code quality. Experimental data show that state-of-the-art DBT products have dynamic code inflation of at least 1.46. This indicates that on average, more than 1.46 host instructions are needed to emulate one guest instruction. Worse, inflation closely correlates with translated code quality. However, the detailed sources of instruction inflation remain unclear. To understand the sources of inflation, we present Deflater , an instruction inflation analysis framework comprising a mathematical model, a collection of black-box unit tests called BenchMIAOes , and a trace-based simulator called InflatSim . The mathematical model calculates overall inflation based on the inflation of individual instructions and translation block optimizations. BenchMIAOes extract model parameters from DBTs without accessing DBT source code. InflatSim implements the model and uses the extracted parameters from BenchMIAOes to simulate a given DBT’s behavior. Deflater is a valuable tool to guide DBT analysis and improvement. Using Deflater, we simulated inflation for three state-of-the-art CISC-to-RISC DBTs: ExaGear, Rosetta2, and LATX, with inflation errors of 5.63%, 5.15%, and 3.44%, respectively for SPEC CPU 2017, gaining insights into these commercial DBTs. Deflater also efficiently models inflation for the open source DBT QEMU and suggests optimizations that can substantially reduce inflation. Implementing the suggested optimizations confirms Deflater’s effective guidance, with 4.65% inflation error, and gains 5.47x performance improvement.

Exploring Attentional Dynamics in Animated Programming Environments: Trajectories, Variability, and Predictors

Researchers have proposed that the ability to pay attention to teachers’ instruction is a prerequisite for learning. However, meaningful learning is often challenged by the presence of rule-breaking behaviors. In this study, we argue that although students exhibit different attention-related behaviors in all instructional settings, some behaviors are unique to a typical classroom. It is still unclear what factors uniquely determine students’ attention-related behaviors in animated programming environments because of the paucity of research evidence in this area. This study investigates students’ attention-related behaviors during animated programming instruction, including attentional growth trajectory, the nature of differences in attention-related behaviors, and predictors of these behaviors. Our analysis involved 8 classroom videos that collected the programming activities of 30 university students in our previous study. The video files were annotated on a one-dimensional, continuous scale, yielding 1,920 timestamped data points. The data on attentional trajectories and differences in attention-related behaviors were analyzed using latent and multi-level growth modeling, respectively, while data focusing on the predictors of attentional processes were analyzed using the Random Forest machine learning algorithm. We found that students’ attentional growth trajectory is linear and accelerates toward on-task events. However, these behaviors vary within and between students, leading to differences in attention-related behaviors. The results also revealed that individual and instructional characteristics predict the differences in attention-related behaviors. The findings highlight the importance of structured topics, safe classroom environments, quality instructional support, and interactive multimedia objects that activate students’ memory, eliminate task difficulty, and reduce the amount of mental resources required for meaningful learning.

Grassroots operator search for model edge adaptation using mathematical search space

Hardware-aware Neural Architecture Search (HW-NAS) is increasingly being used to design efficient deep learning architectures. An efficient and flexible search space is crucial to the success of HW-NAS. Current approaches focus on designing a macro-architecture and searching for the architecture’s hyperparameters based on a set of possible values. This approach is biased by the expertise of deep learning (DL) engineers and standard modeling approaches. In this paper, we present a Grassroots Operator Search (GOS) methodology. Our HW-NAS adapts a given model for edge devices by searching for efficient operator replacement. We express each operator as a set of mathematical instructions that capture its behavior. The mathematical instructions are then used as the basis for searching and selecting efficient replacement operators that maintain the accuracy of the original model while reducing computational complexity. Our approach is grassroots since it relies on the mathematical foundations to construct new and efficient operators for DL architectures. We demonstrate on various DL models, that our method consistently outperforms the original models on two edge devices, namely Redmi Note 7S and Raspberry Pi3, with a minimum of 2.2x speedup while maintaining high accuracy. Additionally, we showcase a use case of our GOS approach in pulse rate estimation on wristband devices, where we achieve state-of-the-art performance, while maintaining reduced computational complexity, demonstrating the effectiveness of our approach in practical applications.

Darwin3: A large-scale neuromorphic chip with a Novel ISA and On-Chip Learning

Abstract Spiking Neural Networks (SNNs) are gaining increasing attention for their biological plausibility and potential for improved computational efficiency. To match the high spatial-temporal dynamics in SNNs, neuromorphic chips are highly desired to execute SNNs in hardware-based neuron and synapse circuits directly. This paper presents a large-scale neuromorphic chip named Darwin3 with a novel instruction set architecture(ISA), which comprises 10 primary instructions and a few extended instructions. It supports flexible neuron model programming and local learning rule designs. The Darwin3 chip architecture is designed in a mesh of computing nodes with an innovative routing algorithm. We used a compression mechanism to represent synaptic connections, significantly reducing memory usage. The Darwin3 chip supports up to 2.35 million neurons, making it the largest of its kind in neuron scale. The experimental results showed that code density was improved up to 28.3x in Darwin3, and neuron core fan-in and fan-out were improved up to 4096x and 3072x by connection compression compared to the physical memory depth. Our Darwin3 chip also provided memory saving between 6.8X and 200.8X when mapping convolutional spiking neural networks (CSNN) onto the chip, demonstrating state-of-the-art performance in accuracy and latency compared to other neuromorphic chips.

Challenges of Teaching Reading: A Case of University English Reading Courses

The centrality of reading in students’ academic performance has been well-established in the literature. As a learned skill, reading is acquired in an instructional setting and students’ ability to comprehend and interact with texts is largely shaped by reading instruction. The efficacy of reading instruction is subject to varied factors that stand as challenges to be overcome. This study aimed to explore the challenges experienced by university teachers in teaching reading to B.Ed. English major students. To this end, the study adopted a case study design that comprised purposively selected four university English teachers teaching English reading courses at a constituent campus of Tribhuvan University, and eight B.Ed. English majors from the same campus. The data were collected through a combination of three qualitative methods: classroom observation, semi-structured interview and focus group discussion. The findings revealed students having no coursebooks and relying on other substandard reading materials, students’ poor reading habits, students’ limited vocabulary knowledge, strategically untrained students, and the length of courses and texts as major challenges faced by teachers in teaching the prescribed reading courses. Drawing on these findings, implications for reading pedagogy are considered.

Compact Instruction Set Extensions for Dilithium

Post-quantum cryptography is considered to provide security against both traditional and quantum computer attacks. Dilithium is a digital signature algorithm that derives its security from the challenge of finding short vectors in lattices. It has been selected as one of the standardizations in the NIST post-quantum cryptography project. Hardware-software co-design is a commonly adopted implementation strategy to address various implementation challenges, including limited resources, high performance, and flexibility requirements. In this study, we investigate using compact instruction set extensions (ISEs) for Dilithium, aiming to improve software efficiency with low hardware overheads. To begin with, we propose tightly coupled accelerators that are deeply integrated into the RISC-V processor. These accelerators target the most computationally demanding components in resource-constrained processors, such as polynomial generation, Number Theoretic Transform (NTT), and modular arithmetic. Next, we design a set of custom instructions that seamlessly integrate with the RISC-V base instruction formats, completing the accelerators in a compact manner. Subsequently, we implement our ISEs in a chip design for the Hummingbird E203 core and conduct performance benchmarks for Dilithium utilizing these ISEs. Additionally, we evaluate the resource consumption of the ISEs on FPGA and ASIC technologies. Compared to the reference software implementation on the RISC-V core, our co-design demonstrates a remarkable speedup factor ranging from 6.95 to 9.96. This significant improvement in performance is achieved by incorporating additional hardware resources, specifically, a 35% increase in LUTs, a 14% increase in FFs, 7 additional DSPs, and no additional RAM. Furthermore, compared to the state-of-the-art approach, our work achieves faster speed performance with a reduced circuit cost. Specifically, the usage of additional LUTs, FFs, and RAMs is reduced by 47.53%, 50.43%, and 100%, respectively. On ASIC technology, our approach demonstrates 12, 412 cell counts. Our co-design provides a better tradeoff implementation on speed performance and circuit overheads.

Wireless vision-based digital media fixed-point DSP processor depending robots for natural calamities

Abstract Natural calamities are affecting many parts of the world. Natural disasters, terrorist attacks, earthquakes, wildfires, floods and all unpredicted phenomena. Disasters cause emergency conditions, so imperative to coordinate the prompt delivery of essential services to the sufferers. Often, disasters lead many people to perish by becoming trapped inside, but many more also perish as a result of individuals receiving rescue either too late or not at all. The implementation and design of a Receiver module utilizing Davinci code processor DVM6437, Wireless camera receiver, Zigbee Transceiver and Global Positioning System (GPS) is proposed in this manuscript for Wireless Vision-based Semi-Autonomous rescue robots that are employed in rough terrain. The receiver side’s Zigbee transceiver module eliminates the limitations of tele-operating rescue robots by enabling the control station to receive GPS data signals and aids in robot management by sending control signals wirelessly. Half and full-duplex communication are supported by the Davinci processor DVM6437, a digital media fixed-point DSP processor that relies on Very Long Instruction Words. It includes an extensive instruction set that is ideal for real-time salvage operations. DVM processor is coded utilizing MATLAB Simulink. MATLAB codes and Simulink blocks are employed under Embedded IDE link.

A genetic programming approach to the automated design of CNN models for image classification and video shorts creation

Neural architecture search (NAS) is a rapidly growing field which focuses on the automated design of neural network architectures. Genetic algorithms (GAs) have been predominantly used for evolving neural network architectures. Genetic programming (GP), a variation of GAs that work in the program space rather than a solution space, has not been as well researched for NAS. This paper aims to contribute to the research into GP for NAS. Previous research in this field can be divided into two categories. In the first each program represents neural networks directly or components and parameters of neural networks. In the second category each program is a set of instructions, which when executed, produces a neural network. This study focuses on this second category which has not been well researched. Previous work has used grammatical evolution for generating these programs. This study examines canonical GP for neural network design (GPNND) for this purpose. It also evaluates a variation of GP, iterative structure-based GP (ISBGP) for evolving these programs. The study compares the performance of GAs, GPNND and ISBGP for image classification and video shorts creation. Both GPNND and ISBGP were found to outperform GAs, with ISBGP producing better results than GPNND for both applications. Both GPNND and ISBGP produced better results than previous studies employing grammatical evolution on the CIFAR-10 dataset.